MCQs in Linear-Digital ICs

(Last Updated On: December 8, 2017)

This is the Multiple Choice Questions in Linear-Digital ICs from the book Electronic Devices and Circuit Theory 10th Edition by Robert L. Boylestad. If you are looking for a reviewer in Electronics Engineering this will definitely help. I can assure you that this will be a great help in reviewing the book in preparation for your Board Exam. Make sure to familiarize each and every questions to increase the chance of passing the ECE Board Exam.

Online Questions and Answers Topic Outline

• MCQs in Introduction to Digital ICs | MCQs in Comparator Unit Operation | MCQs in Digital-Analog Converters | MCQs in Timer IC Unit Operation | MCQs in Voltage-Controlled Oscillator | MCQs in Phase-Locked Loop | MCQs in Interfacing Circuitry

Practice Exam Test Questions

Choose the letter of the best answer in each questions.

1. Which of the following is not a linear/digital IC?

• A. Phase-locked loop
• B. Voltage-controlled oscillator
• C. Passive filter
• D. Comparator

2. Which of the following circuits is (are) linear/digital ICs?

• A. Comparators
• B. Timers
• C. Voltage-controlled oscillators
• D. All of the above

3. Which of the following is (are) the results of improvements built into a comparator IC?

• A. Faster switching between the two output levels
• B. Noise immunity
• C. Outputs capable of directly driving a variety of loads
• D. All of the above

4. How many comparators does a 339 IC contain?

• A. 4
• B. 3
• C. 2
• D. 1

5. This circuit is an example of a ______.

• A. comparator
• B. 555 timer
• C. D to A converter

6. A 311 IC is an example of an eight-pin DIP that can be made to function as a _____.

• A. comparator
• B. 555 timer
• C. D to A converter

7. A 339 IC is an example of a fourteen-pin DIP that can be made to function as a _____.

• A. comparator
• B. 555 timer
• C. D to A converter

8. What is the function of a ladder network?

• A. Changing an analog signal to a digital signal
• B. Changing a linear signal to a digital signal
• C. Changing a digital signal to an analog signal
• D. None of the above

9. What is (are) the level(s) of the input voltage to a ladder-network conversion?

• A. 0
• B. Vref
• C. 0 V or Vref
• D. None of the above

10. What is the level of the output voltage of a ladder-network conversion?

• A. The analog output voltage proportional to the digital input voltage
• B. The digital output voltage proportional to the linear input voltage
• C. A fixed digital value Vref
• D. A fixed analog value Vref

11. What is the voltage resolution of an 8-stage ladder network?

• A. Vref /128
• B. Vref /256
• C. Vref /512
• D. Vref /1024

12. Which of the slope intervals of the integrator does the counter in the analog-to-digital converter (ADC) operate?

• A. Positive
• B. Negative
• C. Both positive and negative
• D. Neither positive nor negative

13. What is the first phase of the dual-slope method of conversion?

• A. Connecting the analog voltage to the integrator for a fixed time
• B. Setting the counter to zero
• C. Connecting the integrator to a reference voltage
• D. All of the above

14. When is the counter set to zero in the dual-slope method of conversion?

• A. Prior to the charging of the capacitor of the integrator
• B. While the capacitor is being charged
• C. At the end of the charging of the capacitor
• D. During the discharging of the capacitor

15. Which of the following devices is (are) a component of a digital-to-analog converter (DAC)?

• A. Integrator
• B. Comparator
• C. Digital counter
• D. All of the above

16. At which of the following period(s) is the counter advanced (incremented) in dual-slope conversion?

• A. During the charging of the capacitor of the integrator
• B. During the discharging of the capacitor of the integrator
• C. During both the charging and discharging of the capacitor of the integrator
• D. None of the above

17. What is (are) the input(s) to the comparator in the ladder-network conversion of an ADC?

• A. Staircase voltage
• D. None of the above

18. What is the maximum conversion time of a clock rate of 1 MHz operating a 10-stage counter in an ADC?

• A. 1.024 s
• B. 102.3 ms
• C. 10.24 ms
• D. 1.024 ms

19. What is the minimum number of conversions per second of a clock rate of 1 MHz operating a 10-stage counter in an ADC?

• A. 1000
• B. 976
• C. 769
• D. 697

20. On which of the following does the conversion depend in ladder-network conversion?

• A. Comparator
• B. Control logic
• C. Digital counter
• D. Clock

21. This circuit is an example of a _____.

• A. comparator
• B. 555 timer
• C. D to A converter

22. This figure is a block diagram of a(n) _____.

• B. DAC
• C. comparator
• D. 555 timer

23. Calculate the frequency of this circuit.

• A. 635 Hz
• B. 450 Hz
• C. 228 Hz
• D. 128 Hz

24. The 555 timer IC is made up of a combination of linear comparators and digital flip-flops.

• A. True
• B. False

25. Which application best describes this 555 timer circuit?

• A. Monostable multivibrator
• B. Astable multivibrator
• C. Bistable multivibrator
• D. One-shot multivibrator

26. Which application best describes this 555 timer circuit?

• A. Monostable multivibrator
• B. Astable multivibrator
• C. Bistable multivibrator
• D. Free-running multivibrator

27. Which of the following best describes the output of a 566 voltage-controlled oscillator?

• A. Square-wave
• B. Triangular-wave
• C. Both square- and triangular-wave
• D. None of the above

28. Which of the following best describes limitations for the 566 VCO?

• A. 2 kΩ ≤ R1 ≤ 20 kΩ
• B. 0.75 V+ ≤ Vc ≤+
• C. fo < 1 MHz
• D. All of the above

29. Determine the free-running frequency for this circuit.

• A. 32.5 kHz
• B. 53.33 kHz
• C. 533.3 kHz
• D. 5.3 MHz

30. Determine the free-running frequency when R3 is set to 2.5 kΩ.

• A. 19.7 kHz
• B. 32.5 kHz
• C. 116.39 kHz
• D. 212.9 kHz

31. The voltage-controlled oscillator is a subset of the "test bench" function generator.

• A. True
• B. False

32. Which of the following applications include a phase-locked loop (PLL) circuit?

• A. Modems
• B. Am decoders
• C. Tracking filters
• D. All of the above

33. How many Vcc connections does the 565 PLL use?

• A. 0
• B. 1
• C. 2
• D. 3

34. The timing components for a PLL are 15 kΩ and 220 pF. Calculate the free-running frequency.

• A. 90.91 kHz
• B. 136.36 kHz
• C. 156.1 kHz
• D. 181.8 kHz

35. Which of the following frequencies is associated with the 565 frequency-shift keyed decoder?

• A. 1070 Hz
• B. 1270 Hz
• C. Both 1070 Hz and 1270 Hz
• D None of the above

FILL-IN-THE-BLANKS

1. A comparator circuit accepts input of _____ voltages and provides a _____ output that indicates when one input is less than or greater than the second.

• A. linear, digital
• B. linear, linear
• C. digital, linear
• D. None of the above

2. In a comparator, the reference voltage is connected to _____ input terminal and the input signal is applied to _____ input terminal.

• A. only the minus, only the plus
• B. only the plus, only the minus
• C. either the plus or minus, the other
• D. None of the above

3. In a comparator, the level of the reference voltage must be _____.

• A. negative
• B. positive
• C. zero
• D. All of the above

4. The 311 voltage comparator can operate from _____.

• A. dual power supplies of 15 V
• B. a single +5 V supply
• C. either a dual power supply of 15 V or a single +5 V supply
• D. None of the above

5. When the input to the 311 voltage comparator is _____ value, the output is _____ if the inverting input is connected to ground.

• A. any negative, low
• B. any positive, low
• C. any positive, high
• D. None of the above

6. In the operation of two 311 voltage comparators as the voltage window detector, a high output indicates that the input is _____.

• A. above the higher reference voltage
• B. below the lower reference voltage
• C. either above the higher reference voltage or below the lower reference voltage
• D. within the high and the low reference voltages

7. In the operation of two 311 voltage comparators as the voltage window detector, a low output indicates that the input is _____.

• A. above the higher reference voltage
• B. below the lower reference voltage
• C. either above the higher reference voltage or below the lower reference voltage
• D. within the high and the low reference voltages

8. In a ladder-network conversion, _____ ladder stages provide _____ voltage resolution.

• A. more, greater
• B. more, smaller
• C. fewer, greater
• D. None of the above

9. In a ladder-network conversion, the _____ circuit provides a signal to stop the counter when the staircase voltage rises above the input voltage.

• A. control logic
• B. comparator
• D. None of the above

10. The conversion resolution of an 8-stage counter operating an 8-stage ladder network using a reference voltage of 5 V is _____.

• A. 0.0195 mV
• B. 0.195 mV
• C. 1.95 mV
• D. 19.5 mV

11. In a 555 timer, a series connection of three resistors sets the reference voltage levels to the two comparators at _____ and __________.

• A. 2VCC / 3, VCC / 3
• B. VCC / 2, VCC / 4
• C. VCC, VCC / 2
• D. VCC, VCC

12. In astable operation of the 555 timer, the external capacitor, C, is charged through external resistor(s) _____ and is discharged through resistor(s) _____.

• A. RA, RA
• B. RB, RA
• C. RA and RB, RB
• D. RB, RA and RB

13. In astable operation of the 555 timer, the lower and upper peaks of the charging/discharging external capacitor are _____ to _____.

• A. –VCC, VCC
• B. –0.5 VCC, 0.5 VCC
• C. 1/3 VCC, 1/2 VCC
• D. 1/3 VCC, 2/3 VCC

14. Time periods for monostable operation of the 555 timer can range from _____ to _____, making this IC useful for a range of applications.

• A. picoseconds, nanoseconds
• B. nanoseconds, milliseconds
• C. microseconds, many seconds
• D. None of the above

15. A voltage-controlled oscillator (VCO) is a circuit that provides a _____ output signal.

• A. zero
• B. varying
• C. constant
• D. None of the above

16. The frequency of the 566 VCO is set by _____.

• A. an external resistor
• B. an external capacitor
• C. both an external resistor and an external capacitor
• D. None of the above

17. A phase-locked loop (PLL) is an electronic circuit that consists of _____.

• A. a phase detector
• B. a low-pass filter
• C. a voltage-controlled oscillator
• D. All of the above

18. When the loop is in lock in a PLL, the input frequency is _____ the output frequency from the VCO.

• A. the same as
• B. greater than
• C. smaller than
• D. None of the above

19. In the frequency-shift keyed (FSK) signal decoder, the RC ladder filter is used to _____.

• A. remove the difference frequency component
• B. remove the sum frequency component
• C. remove both the difference and the sum frequency components
• D. None of the above

20. The free-running frequency of a 565 FSK decoder is adjusted with _____.

• A. external capacitors
• B. an external resistor
• C. an external RC network
• D. an internal clock

21. An input at a frequency of 1070 Hz will drive the decoder output voltage to _____.

• A. –5 V
• B. 14 V
• C. –5 V and 14 V
• D. None of the above

22. In interfacing circuitry, a receiver provides _____ input impedance to minimize loading of the input signal.

• A. high
• B. medium
• C. low
• D. zero

23. For transistor transistor logic (TTL) circuits, _____ is a mark and _____ is a space.

• A. 12 V, 0 V
• B. 0 V, 12 V
• C. 0 V, 5 V
• D. 5 V, 0 V

24. For the RS-232C circuit, _____ is a mark and _____ is a space.

• A. 12 V, –12 V
• B. –12 V, 12 V
• C. 5 V, 0 V
• D. –5 V, 0 V

25. Which of the following require(s) interfacing circuitry?

• A. Keyboards
• B. Video terminals
• C. Printers
• D. All of the above

Complete List of Chapter Quiz in Electronic Devices and Circuit Theory

MCQs in Linear-Digital ICs
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