 # Boylestad: MCQ in Linear-Digital ICs

(Last Updated On: August 13, 2019) This is the Multiple Choice Questions in Linear-Digital ICs from the book Electronic Devices and Circuit Theory 10th Edition by Robert L. Boylestad. If you are looking for a reviewer in Electronics Engineering this will definitely help. I can assure you that this will be a great help in reviewing the book in preparation for your Board Exam. Make sure to familiarize each and every questions to increase the chance of passing the ECE Board Exam.

#### Online Questions and Answers Topic Outline

• MCQ in Introduction to Digital ICs | MCQ in Comparator Unit Operation | MCQ in Digital-Analog Converters | MCQ in Timer IC Unit Operation | MCQ in Voltage-Controlled Oscillator | MCQ in Phase-Locked Loop | MCQ in Interfacing Circuitry

#### Practice Exam Test Questions

Choose the letter of the best answer in each questions.

1. Which of the following is not a linear/digital IC?

A. Phase-locked loop

B. Voltage-controlled oscillator

C. Passive filter

D. Comparator

Solution:

2. Which of the following circuits is (are) linear/digital ICs?

A. Comparators

B. Timers

C. Voltage-controlled oscillators

D. All of the above

Solution:

3. Which of the following is (are) the results of improvements built into a comparator IC?

A. Faster switching between the two output levels

B. Noise immunity

C. Outputs capable of directly driving a variety of loads

D. All of the above

Solution:

4. How many comparators does a 339 IC contain?

A. 4

B. 3

C. 2

D. 1

Solution:

5. This circuit is an example of a ________. A. comparator

B. 555 timer

C. D to A converter

Solution:

6. A 311 IC is an example of an eight-pin DIP that can be made to function as a _______.

A. comparator

B. 555 timer

C. D to A converter

Solution:

7. A 339 IC is an example of a fourteen-pin DIP that can be made to function as a _______.

A. comparator

B. 555 timer

C. D to A converter

Solution:

8. What is the function of a ladder network?

A. Changing an analog signal to a digital signal

B. Changing a linear signal to a digital signal

C. Changing a digital signal to an analog signal

D. None of the above

Solution:

9. What is (are) the level(s) of the input voltage to a ladder-network conversion?

A. 0

B. Vref

C. 0 V or Vref

D. None of the above

Solution:

10. What is the level of the output voltage of a ladder-network conversion?

A. The analog output voltage proportional to the digital input voltage

B. The digital output voltage proportional to the linear input voltage

C. A fixed digital value Vref

D. A fixed analog value Vref

Solution:

11. What is the voltage resolution of an 8-stage ladder network?

A. Vref /128

B. Vref /256

C. Vref /512

D. Vref /1024

Solution:

12. Which of the slope intervals of the integrator does the counter in the analog-to-digital converter (ADC) operate?

A. Positive

B. Negative

C. Both positive and negative

D. Neither positive nor negative

Solution:

13. What is the first phase of the dual-slope method of conversion?

A. Connecting the analog voltage to the integrator for a fixed time

B. Setting the counter to zero

C. Connecting the integrator to a reference voltage

D. All of the above

Solution:

14. When is the counter set to zero in the dual-slope method of conversion?

A. Prior to the charging of the capacitor of the integrator

B. While the capacitor is being charged

C. At the end of the charging of the capacitor

D. During the discharging of the capacitor

Solution:

15. Which of the following devices is (are) a component of a digital-to-analog converter (DAC)?

A. Integrator

B. Comparator

C. Digital counter

D. All of the above

Solution:

16. At which of the following period(s) is the counter advanced (incremented) in dual-slope conversion?

A. During the charging of the capacitor of the integrator

B. During the discharging of the capacitor of the integrator

C. During both the charging and discharging of the capacitor of the integrator

D. None of the above

Solution:

17. What is (are) the input(s) to the comparator in the ladder-network conversion of an ADC?

A. Staircase voltage

D. None of the above

Solution:

18. What is the maximum conversion time of a clock rate of 1 MHz operating a 10-stage counter in an ADC?

A. 1.024 s

B. 102.3 ms

C. 10.24 ms

D. 1.024 ms

Solution:

19. What is the minimum number of conversions per second of a clock rate of 1 MHz operating a 10-stage counter in an ADC?

A. 1000

B. 976

C. 769

D. 697

Solution:

20. On which of the following does the conversion depend in ladder-network conversion?

A. Comparator

B. Control logic

C. Digital counter

D. Clock

Solution:

21. This circuit is an example of a ________. A. comparator

B. 555 timer

C. D to A converter

Solution:

22. This figure is a block diagram of a(n) _______. B. DAC

C. comparator

D. 555 timer

Solution:

23. Calculate the frequency of this circuit. A. 635 Hz

B. 450 Hz

C. 228 Hz

D. 128 Hz

Solution:

24. The 555 timer IC is made up of a combination of linear comparators and digital flip-flops.

A. True

B. False

Solution:

25. Which application best describes this 555 timer circuit? A. Monostable multivibrator

B. Astable multivibrator

C. Bistable multivibrator

D. One-shot multivibrator

Solution:

26. Which application best describes this 555 timer circuit? A. Monostable multivibrator

B. Astable multivibrator

C. Bistable multivibrator

D. Free-running multivibrator

Solution:

27. Which of the following best describes the output of a 566 voltage-controlled oscillator?

A. Square-wave

B. Triangular-wave

C. Both square- and triangular-wave

D. None of the above

Solution:

28. Which of the following best describes limitations for the 566 VCO?

A. 2 kΩ ≤ R1 ≤ 20 kΩ

B. 0.75 V+ ≤ Vc ≤+

Solution:

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29. Determine the free-running frequency for this circuit. A. 32.5 kHz

B. 53.33 kHz

C. 533.3 kHz

D. 5.3 MHz

Solution:

30. Determine the free-running frequency when R3 is set to 2.5 kΩ. A. 19.7 kHz

B. 32.5 kHz

C. 116.39 kHz

D. 212.9 kHz

Solution:

31. The voltage-controlled oscillator is a subset of the “test bench” function generator.

A. True

B. False

Solution:

32. Which of the following applications include a phase-locked loop (PLL) circuit?

A. Modems

B. Am decoders

C. Tracking filters

D. All of the above

Solution:

33. How many Vcc connections does the 565 PLL use?

A. 0

B. 1

C. 2

D. 3

Solution:

34. The timing components for a PLL are 15 kΩ and 220 pF. Calculate the free-running frequency.

A. 90.91 kHz

B. 136.36 kHz

C. 156.1 kHz

D. 181.8 kHz

Solution:

35. Which of the following frequencies is associated with the 565 frequency-shift keyed decoder?

A. 1070 Hz

B. 1270 Hz

C. Both 1070 Hz and 1270 Hz

D None of the above

Solution:

#### FILL-IN-THE-BLANKS

1. A comparator circuit accepts input of _______ voltages and provides a _______ output that indicates when one input is less than or greater than the second.

A. linear, digital

B. linear, linear

C. digital, linear

D. None of the above

Solution:

2. In a comparator, the reference voltage is connected to _______ input terminal and the input signal is applied to _______ input terminal.

A. only the minus, only the plus

B. only the plus, only the minus

C. either the plus or minus, the other

D. None of the above

Solution:

3. In a comparator, the level of the reference voltage must be _______.

A. negative

B. positive

C. zero

D. All of the above

Solution:

4. The 311 voltage comparator can operate from _______.

A. dual power supplies of 15 V

B. a single +5 V supply

C. either a dual power supply of 15 V or a single +5 V supply

D. None of the above

Solution:

5. When the input to the 311 voltage comparator is _______ value, the output is _______ if the inverting input is connected to ground.

A. any negative, low

B. any positive, low

C. any positive, high

D. None of the above

Solution:

6. In the operation of two 311 voltage comparators as the voltage window detector, a high output indicates that the input is _______.

A. above the higher reference voltage

B. below the lower reference voltage

C. either above the higher reference voltage or below the lower reference voltage

D. within the high and the low reference voltages

Solution:

7. In the operation of two 311 voltage comparators as the voltage window detector, a low output indicates that the input is _______.

A. above the higher reference voltage

B. below the lower reference voltage

C. either above the higher reference voltage or below the lower reference voltage

D. within the high and the low reference voltages

Solution:

8. In a ladder-network conversion, _______ ladder stages provide _______ voltage resolution.

A. more, greater

B. more, smaller

C. fewer, greater

D. None of the above

Solution:

9. In a ladder-network conversion, the _______ circuit provides a signal to stop the counter when the staircase voltage rises above the input voltage.

A. control logic

B. comparator

D. None of the above

Solution:

10. The conversion resolution of an 8-stage counter operating an 8-stage ladder network using a reference voltage of 5 V is _______.

A. 0.0195 mV

B. 0.195 mV

C. 1.95 mV

D. 19.5 mV

Solution:

11. In a 555 timer, a series connection of three resistors sets the reference voltage levels to the two comparators at _______ and __________.

A. 2VCC/3, VCC/3

B. VCC/2, VCC/4

C. VCC, VCC/2

D. VCC, VCC

Solution:

12. In astable operation of the 555 timer, the external capacitor, C, is charged through external resistor(s) _______ and is discharged through resistor(s) _______. A. RA, RA

B. RB, RA

C. RA and RB, RB

D. RB, RA and RB

Solution:

13. In astable operation of the 555 timer, the lower and upper peaks of the charging/discharging external capacitor are _______ to _______.

A. –VCC, VCC

B. –0.5 VCC, 0.5 VCC

C. 1/3 VCC, 1/2 VCC

D. 1/3 VCC, 2/3 VCC

Solution:

14. Time periods for monostable operation of the 555 timer can range from _______ to _______, making this IC useful for a range of applications.

A. picoseconds, nanoseconds

B. nanoseconds, milliseconds

C. microseconds, many seconds

D. None of the above

Solution:

15. A voltage-controlled oscillator (VCO) is a circuit that provides a _______ output signal.

A. zero

B. varying

C. constant

D. None of the above

Solution:

16. The frequency of the 566 VCO is set by _______.

A. an external resistor

B. an external capacitor

C. both an external resistor and an external capacitor

D. None of the above

Solution:

17. A phase-locked loop (PLL) is an electronic circuit that consists of _______.

A. a phase detector

B. a low-pass filter

C. a voltage-controlled oscillator

D. All of the above

Solution:

18. When the loop is in lock in a PLL, the input frequency is _______ the output frequency from the VCO.

A. the same as

B. greater than

C. smaller than

D. None of the above

Solution:

19. In the frequency-shift keyed (FSK) signal decoder, the RC ladder filter is used to _______.

A. remove the difference frequency component

B. remove the sum frequency component

C. remove both the difference and the sum frequency components

D. None of the above

Solution:

20. The free-running frequency of a 565 FSK decoder is adjusted with _______.

A. external capacitors

B. an external resistor

C. an external RC network

D. an internal clock

Solution:

21. An input at a frequency of 1070 Hz will drive the decoder output voltage to _______.

A. –5 V

B. 14 V

C. –5 V and 14 V

D. None of the above

Solution:

22. In interfacing circuitry, a receiver provides _______ input impedance to minimize loading of the input signal.

A. high

B. medium

C. low

D. zero

Solution:

23. For transistor transistor logic (TTL) circuits, _______ is a mark and _______ is a space.

A. 12 V, 0 V

B. 0 V, 12 V

C. 0 V, 5 V

D. 5 V, 0 V

Solution:

24. For the RS-232C circuit, _______ is a mark and _______ is a space.

A. 12 V, –12 V

B. –12 V, 12 V

C. 5 V, 0 V

D. –5 V, 0 V

Solution:

25. Which of the following require(s) interfacing circuitry?

A. Keyboards

B. Video terminals

C. Printers

D. All of the above

Solution: 