201+ Essential Microprocessor Terms Every Engineering Board Exam Candidate Must Master

If you’re preparing for your engineering board exams, you know that mastering microprocessor concepts isn’t just another topic to study—it’s often the difference between passing and failing. Many engineering students struggle with the massive scope of microprocessor terminology, finding themselves overwhelmed by technical jargon that seems to blur together as exam day approaches. I’ve been there too, flipping through textbooks at 2 AM, wondering how anyone could possibly memorize all these terms.

That’s exactly why I’ve compiled this comprehensive guide of 201+ microprocessor terms and definitions specifically designed for board exam success. This isn’t just another glossary—it’s organized into logical sections that follow the way examiners actually create questions, focusing on terms that have consistently appeared in previous board exams. Whether you’re struggling with the fundamentals of processor architecture or confused about the difference between various memory addressing modes, this guide has you covered.

Many students tell me they waste precious study time searching through multiple sources to piece together definitions, often ending up with conflicting explanations. This collection solves that problem by providing clear, concise, and exam-focused definitions all in one place. So grab your highlighter, bookmark this page, and let’s transform microprocessor terminology from your biggest weakness into your secret weapon for acing the board exam.

Basic Microprocessor Concepts

1. Microprocessor: An integrated circuit that contains the arithmetic, logic, and control circuitry required to perform the functions of a computer’s central processing unit.

2. Central Processing Unit (CPU): The primary component of a computer that performs most of the processing inside a computer.

3. Instruction Set: The complete set of instructions that a microprocessor can execute, defining its capabilities and programming model.

4. Word Size: The number of bits processed by a microprocessor in a single operation, commonly 8, 16, 32, or 64 bits.

5. Clock Speed: The frequency at which a microprocessor executes instructions, measured in Hertz (Hz), Megahertz (MHz), or Gigahertz (GHz).

6. Clock Cycle: The smallest unit of time in which a microprocessor performs a basic operation.

7. Machine Cycle: The sequence of operations that a microprocessor performs to execute a single machine language instruction.

8. Fetch-Decode-Execute Cycle: The basic operational cycle of a CPU where instructions are fetched from memory, decoded into commands, and then executed.

9. RISC: Reduced Instruction Set Computer – a microprocessor design philosophy that uses a small, highly optimized set of instructions.

10. CISC: Complex Instruction Set Computer – a microprocessor design that incorporates many specialized instructions, some of which may perform several low-level operations.

11. Von Neumann Architecture: A computer design where the same memory and data paths are used to store both program instructions and data.

12. Harvard Architecture: A computer architecture with physically separate storage and signal pathways for instructions and data.

13. Modified Harvard Architecture: A variation of the Harvard architecture where the instruction and data memories are separate but can share information through a common bus.

14. Microcode: A layer of hardware-level instructions used to implement higher-level machine code instructions.

15. Nanoprogramming: The lowest level of machine programming, implementing microcode instructions directly in hardware.

16. Microcoded Design: A processor design where complex instructions are implemented using simpler microcode instructions.

17. Hardwired Control: A control unit implementation using fixed logic circuits rather than microcoded instructions.

18. Microinstruction: A low-level instruction used in microcode to control the datapath of a CPU.

Microprocessor Components

19. Arithmetic Logic Unit (ALU): The digital circuit within the microprocessor that performs arithmetic and logical operations.

20. Control Unit: The part of the CPU that directs the operation of the processor by telling the computer’s memory, ALU, and input/output devices how to respond to program instructions.

21. Registers: Small, high-speed storage areas within the microprocessor used to store temporary data during processing.

22. Accumulator: A special register that stores the results of arithmetic and logical operations.

23. Program Counter (PC): A register that contains the address of the next instruction to be executed.

24. Stack Pointer: A register that points to the top of the stack in memory where temporary data is stored.

25. Status Register: A register that contains flags indicating the status of operations performed by the ALU.

26. Instruction Register: A register that temporarily holds the instruction currently being decoded and executed.

27. Address Bus: A group of electrical conductors used to transfer memory addresses from the CPU to other components.

28. Data Bus: A system of electrical conductors that transfers data between the CPU, memory, and peripherals.

29. Control Bus: A collection of control lines that the CPU uses to coordinate its operations with other components.

30. General Purpose Registers: Registers that can be used for any purpose by the programmer or compiler.

31. Special Purpose Registers: Registers designed for specific functions within the processor.

32. Index Register: A register used to modify operand addresses during program execution.

33. Base Register: A register that holds a base address used in relative addressing.

34. Memory Address Register (MAR): A register that holds the memory address from which data will be fetched or to which data will be sent.

35. Memory Data Register (MDR): A register that holds data being transferred to or from memory.

36. Memory Buffer Register (MBR): A register that temporarily stores data during memory operations.

37. Flag Register: A register containing bits that indicate specific conditions resulting from an instruction execution.

38. Carry Flag: A flag that indicates when an arithmetic operation generates a carry or borrow.

39. Zero Flag: A flag that indicates when the result of an operation is zero.

40. Sign Flag: A flag that indicates whether the result of an operation is positive or negative.

41. Overflow Flag: A flag that indicates when the result of an arithmetic operation exceeds the capacity of the destination.

42. Parity Flag: A flag that indicates whether the number of set bits in a result contains an even or odd number of 1’s.

Microprocessor Architecture

43. Pipelining: A technique that allows multiple instructions to be overlapped during execution, improving throughput.

44. Superscalar Architecture: A design that allows multiple instructions to be executed simultaneously in parallel execution units.

45. Multicore Processor: A single computing component with two or more independent processor cores.

46. Branch Prediction: A technique used by processors to guess the outcome of a conditional branch instruction before it is executed.

47. Cache Memory: A smaller, faster memory located closer to the CPU that stores copies of frequently used data from main memory.

48. Translation Lookaside Buffer (TLB): A cache that memory management hardware uses to improve virtual address translation speed.

49. Memory Management Unit (MMU): A hardware component responsible for handling memory access requested by the CPU.

50. Interrupt Controller: A circuit that prioritizes and manages interrupts sent to the CPU.

51. Direct Memory Access (DMA): A feature that allows certain hardware subsystems to access main system memory independently of the CPU.

52. Memory-Mapped I/O: A method of performing input/output operations where devices share the same address space as the main memory.

53. Port-Mapped I/O: A method where input/output devices are accessed through a dedicated I/O address space separate from memory.

54. Pipeline Stage: One step in the pipeline process, such as fetch, decode, execute, memory access, or write-back.

55. Pipeline Depth: The number of stages in a processor pipeline.

56. Scalar Processor: A processor that executes one instruction at a time.

57. Vector Processor: A processor that can perform the same operation on multiple data elements simultaneously.

58. Very Long Instruction Word (VLIW): A processor architecture that uses instruction-level parallelism by executing multiple operations packed into a single instruction.

59. Explicitly Parallel Instruction Computing (EPIC): An instruction set architecture that allows the compiler to explicitly specify instruction-level parallelism.

60. Simultaneous Multithreading (SMT): A technique that allows multiple independent threads to issue instructions to different execution units in a single cycle.

61. Co-processor: A supplementary processor designed to handle specific tasks, often floating-point calculations.

62. System Bus: The pathway that connects the major components of a computer system, including the CPU, memory, and peripherals.

Memory Systems

63. RAM (Random Access Memory): Volatile memory used to store program data and instructions during execution.

64. ROM (Read-Only Memory): Non-volatile memory containing permanent data that cannot be modified.

65. PROM (Programmable ROM): A form of digital memory where the setting of each bit is locked by a fuse or antifuse.

66. EPROM (Erasable PROM): A type of ROM that can be erased and reprogrammed by exposure to ultraviolet light.

67. EEPROM (Electrically Erasable PROM): A type of non-volatile memory that can be electrically erased and reprogrammed.

68. Flash Memory: A non-volatile memory that can be electrically erased and reprogrammed, commonly used in solid-state drives.

69. Static RAM (SRAM): A type of RAM that retains data bits as long as power is supplied.

70. Dynamic RAM (DRAM): A type of RAM that stores each bit of data in a separate capacitor that must be periodically refreshed.

71. Virtual Memory: A memory management technique that uses both hardware and software to allow a computer to compensate for physical memory shortages.

72. Memory Hierarchy: The arrangement of different memory types in a computer system based on access time, capacity, and cost.

73. Memory Interleaving: A technique for improving memory access by dividing memory into multiple banks that can be accessed simultaneously.

74. Memory Segmentation: A memory management scheme that divides a computer’s memory into segments or sections.

75. Memory Paging: A memory management scheme that divides virtual memory into fixed-size blocks called pages.

76. L1 Cache: The primary cache memory, typically integrated into the processor chip, providing the fastest access to data.

77. L2 Cache: A secondary cache memory, often larger but slower than L1, providing an intermediate level of storage.

78. L3 Cache: A third-level cache, larger but slower than L2, shared among multiple cores in multicore processors.

79. Cache Line: The smallest unit of data that can be transferred between the cache and main memory.

80. Cache Hit: An event that occurs when data requested by the processor is found in the cache.

81. Cache Miss: An event that occurs when data requested by the processor is not found in the cache.

82. Cache Coherence Protocol: Rules that maintain the consistency of data stored in multiple caches.

83. Write-Through Cache: A caching technique where data is written to both the cache and main memory simultaneously.

84. Write-Back Cache: A caching technique where data is written only to the cache and later synchronized with main memory.

85. Memory Protection: Hardware mechanisms that control memory access rights, preventing unauthorized access.

86. Memory Bank: A group of memory chips that are accessed simultaneously to provide a memory word.

87. Memory Controller: A digital circuit that manages the flow of data to and from memory.

88. Refresh Cycle: The process of periodically reading and rewriting data in DRAM to prevent data loss.

89. Memory Access Time: The time it takes from when a memory request is made until the data becomes available.

90. Memory Bandwidth: The rate at which data can be read from or written to memory.

91. Non-Uniform Memory Access (NUMA): A memory design where memory access time depends on the memory location relative to the processor.

92. Error-Correcting Code (ECC) Memory: Memory that includes special circuitry for detecting and correcting memory errors.

Instruction Set Architecture

93. Opcode: The portion of a machine language instruction that specifies the operation to be performed.

94. Operand: The part of an instruction that specifies the data to be operated on.

95. Addressing Mode: The way in which the operand of an instruction is specified.

96. Immediate Addressing: An addressing mode where the operand value is included in the instruction itself.

97. Direct Addressing: An addressing mode where the instruction contains the actual address of the operand.

98. Indirect Addressing: An addressing mode where the instruction contains the address of a memory location that contains the address of the operand.

99. Indexed Addressing: An addressing mode where the effective address is formed by adding an index register to a base address.

100. Register Addressing: An addressing mode where the operand is located in a processor register.

101. Assembly Language: A low-level programming language that provides a symbolic representation of machine code instructions.

102. Machine Language: The lowest-level programming language consisting of binary code that a computer can execute directly.

103. Mnemonic: Symbolic names for machine language instructions used in assembly language.

104. Instruction Format: The layout of bits in a machine instruction, including fields for opcode, addressing mode, and operands.

105. Instruction Cycle Time: The time required to fetch, decode, and execute a single machine instruction.

106. Base-plus-offset Addressing: An addressing mode where the effective address is calculated by adding an offset to a base register.

107. Auto-increment Addressing: An addressing mode where the register value is automatically incremented after being used.

108. Auto-decrement Addressing: An addressing mode where the register value is automatically decremented before being used.

109. Relative Addressing: An addressing mode where the effective address is calculated relative to the program counter.

110. Stack Addressing: An addressing mode that uses the stack pointer to access data on the stack.

111. Displacement Addressing: An addressing mode where the effective address is the sum of a register and a constant.

112. Memory-Indirect Addressing: An addressing mode where the effective address is stored in a memory location pointed to by the instruction.

113. Pre-indexing: An addressing mode where the index is applied before any indirection.

114. Post-indexing: An addressing mode where the index is applied after indirection.

115. Instruction Pointer: A register that indicates the next instruction to be executed, similar to a program counter.

116. Condition Code: A status flag that reflects the result of an arithmetic or logical operation.

Microprocessor Interfacing

117. I/O Interface: Hardware that connects the CPU to external devices, adapting different electrical signals and data formats.

118. Serial Communication: A method of data transmission where bits are sent sequentially over a single communication line.

119. Parallel Communication: A method of data transmission where multiple bits are sent simultaneously over multiple lines.

120. UART (Universal Asynchronous Receiver-Transmitter): A hardware device for asynchronous serial communication.

121. USART (Universal Synchronous/Asynchronous Receiver-Transmitter): A device that can handle both synchronous and asynchronous serial communication.

122. SPI (Serial Peripheral Interface): A synchronous serial communication interface used for short-distance communication.

123. I2C (Inter-Integrated Circuit): A multi-master, multi-slave, single-ended, serial communication bus.

124. USB (Universal Serial Bus): A standard for connecting computers and electronic devices with a focus on simplicity and plug-and-play capability.

125. Interrupt: A signal to the processor indicating that an event needs immediate attention, temporarily suspending normal program execution.

126. Polling: A technique where the processor periodically checks each device to see if it needs servicing.

127. Handshaking: A process of establishing communication between two devices before data transmission begins.

128. Buffer: A temporary storage area used to compensate for differences in data processing speeds between different components.

129. Parallel Port: An interface for connecting an external device that sends or receives data in multiple bits at a time.

130. Serial Port: An interface for connecting an external device that sends or receives data one bit at a time.

131. Maskable Interrupt: An interrupt that can be disabled or ignored by the processor.

132. Non-maskable Interrupt: An interrupt that cannot be disabled and must be processed by the CPU.

133. Interrupt Vector: A memory location that contains the address of an interrupt service routine.

134. Interrupt Service Routine (ISR): A software function that is executed in response to an interrupt.

135. Interrupt Priority: A system that determines which interrupt should be serviced first when multiple interrupts occur simultaneously.

136. Interrupt Mask: A register that allows certain interrupts to be ignored.

137. Programmable Interrupt Controller (PIC): A device that manages multiple interrupt inputs and presents them to the CPU according to priority.

138. Interrupt Acknowledge: A signal from the CPU indicating that it has recognized an interrupt request.

139. Interrupt Latency: The time between when an interrupt is generated and when it is serviced.

140. Programmed I/O: A method of data transfer between the CPU and peripherals where the CPU executes instructions to transfer data.

141. Memory-mapped I/O: A method of performing input/output operations where devices share the same address space as the main memory.

142. Isolated I/O: A method of performing input/output operations where devices are accessed through a dedicated I/O address space.

143. CAN Bus (Controller Area Network): A robust vehicle bus standard designed for microcontrollers to communicate without a host computer.

144. PCI (Peripheral Component Interconnect): A local computer bus for attaching hardware devices in a computer.

145. PCIe (PCI Express): A high-speed serial computer expansion bus standard designed to replace older PCI standards.

146. GPIO (General Purpose Input/Output): Uncommitted digital signal pins on an integrated circuit that can be used as inputs or outputs.

Advanced Topics

147. Pipelining Hazards: Problems that occur in pipelined processors when instructions depend on each other, including data, control, and structural hazards.

148. Speculative Execution: A technique where a processor executes instructions before knowing whether they are actually needed.

149. Out-of-Order Execution: A technique where instructions are executed in an order different from their appearance in the program to improve performance.

150. Register Renaming: A technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers.

151. Instruction-Level Parallelism: A measure of how many operations in a computer program can be performed simultaneously.

152. Thread-Level Parallelism: A form of parallelism where multiple threads exist within the context of a single process and share resources.

153. Vector Processing: A method of executing operations on multiple data elements simultaneously.

154. SIMD (Single Instruction, Multiple Data): A class of parallel computers where multiple processing elements perform the same operation on multiple data points simultaneously.

155. MIMD (Multiple Instruction, Multiple Data): A type of parallel computing architecture where many functional units perform different operations on different data.

156. Cache Coherence: The consistency of shared resource data stored in multiple local caches.

157. Virtual Machine: A software emulation of computer hardware that provides the functionality of a physical computer.

158. Hyperthreading: A technology used to improve parallelization of computations performed on a single microprocessor.

159. Data Hazard: A situation in pipelining where an instruction depends on the result of a previous instruction still in the pipeline.

160. Control Hazard: A situation in pipelining where the flow of instruction execution is changed due to branching, jumping, or other control flow instructions.

161. Structural Hazard: A situation in pipelining where two or more instructions require the same hardware resource simultaneously.

162. Memory Barrier: A type of instruction that causes a processor to enforce an ordering constraint on memory operations.

163. Branch Target Buffer: A specialized cache used to predict the target of a branch instruction.

164. Return Address Stack: A small stack maintained by the processor to predict the target of return instructions.

165. Prefetching: A technique used to fetch instructions or data before they are needed to reduce latency.

166. Software Pipelining: A compiler optimization technique that reschedules operations to achieve better pipeline utilization.

167. Tomasulo’s Algorithm: A hardware algorithm for dynamic scheduling of instructions to allow out-of-order execution.

168. Scoreboarding: A technique used to allow instructions to execute out of order when they are independent.

169. Hardware Multithreading: A technique where multiple threads can be executed concurrently on a single processor core.

170. Fine-grained Multithreading: A form of multithreading where the processor switches between threads after each instruction.

171. Coarse-grained Multithreading: A form of multithreading where the processor switches between threads only on costly stalls.

172. Transactional Memory: A concurrency control mechanism for controlling access to shared memory in concurrent computing.

Microprocessor Evolution and Types

173. 8086: An early 16-bit microprocessor from Intel that established the x86 architecture.

174. ARM Architecture: A family of RISC-based architectures designed for low power consumption, commonly used in mobile devices.

175. x86 Architecture: A family of backward-compatible instruction set architectures based on the Intel 8086 CPU.

176. x64 (x86-64) Architecture: A 64-bit version of the x86 instruction set, supporting larger amounts of virtual and physical memory.

177. MIPS Architecture: A RISC-based architecture used in embedded systems and educational environments.

178. PowerPC: A RISC-based architecture developed by Apple, IBM, and Motorola.

179. System-on-Chip (SoC): An integrated circuit that integrates all components of a computer or other electronic system onto a single chip.

180. Microcontroller: A small computer on a single integrated circuit containing a processor core, memory, and programmable I/O peripherals.

181. Digital Signal Processor (DSP): A specialized microprocessor optimized for digital signal processing operations.

182. Graphics Processing Unit (GPU): A specialized electronic circuit designed to rapidly manipulate and alter memory to accelerate the creation of images for output to a display device.

183. Field-Programmable Gate Array (FPGA): An integrated circuit designed to be configured by a customer or designer after manufacturing.

184. Application-Specific Integrated Circuit (ASIC): An integrated circuit customized for a particular use, rather than intended for general-purpose use.

185. Intel 4004: The first commercially available microprocessor, a 4-bit CPU released in 1971.

186. Z80: An 8-bit microprocessor introduced by Zilog in 1976, widely used in embedded systems and early home computers.

187. Motorola 68000: A 16/32-bit microprocessor used in early Apple Macintosh computers, Amiga, and other systems.

188. IA-64 Architecture: Intel’s 64-bit architecture implemented in the Itanium processor, using explicit parallelism.

189. SPARC (Scalable Processor Architecture): A RISC instruction set architecture developed by Sun Microsystems.

190. Alpha Architecture: A 64-bit RISC instruction set architecture developed by Digital Equipment Corporation.

191. AVR Microcontroller: A family of microcontrollers developed by Atmel, now part of Microchip Technology.

192. PIC Microcontroller: A family of microcontrollers made by Microchip Technology, popular in embedded applications.

193. Neural Processing Unit (NPU): A specialized circuit designed to accelerate machine learning algorithms.

194. Tensor Processing Unit (TPU): A custom ASIC developed by Google specifically for neural network machine learning.

Performance and Optimization

195. CPI (Cycles Per Instruction): The average number of clock cycles per instruction for a program or program fragment.

196. IPC (Instructions Per Cycle): The average number of instructions executed per clock cycle.

197. Throughput: The rate at which a processor can complete processing tasks.

198. Latency: The time delay between the initiation of a process and its completion.

199. Bandwidth: The maximum rate of data transfer across a given path.

200. Amdahl’s Law: A formula that gives the theoretical speedup in latency of the execution of a task at fixed workload when resources are improved.

201. Moore’s Law: An observation that the number of transistors in a dense integrated circuit doubles about every two years.

202. Benchmarking: The act of measuring and assessing the performance of a microprocessor using standard tests.

203. Overclocking: The practice of increasing a component’s clock rate, running it at a higher speed than the manufacturer’s specification.

204. Power Consumption: The amount of electrical energy consumed by a microprocessor per unit time.

205. Thermal Design Power (TDP): The maximum amount of heat generated by a microprocessor that the cooling system is designed to dissipate.

206. Dynamic Voltage and Frequency Scaling (DVFS): A power management technique that adjusts voltage and frequency of a processor based on system workload.

207. Performance per Watt: A measure of the energy efficiency of a particular computer architecture or computer hardware.

208. Cache Hit Ratio: The percentage of memory access requests that result in cache hits.

209. MIPS (Million Instructions Per Second): A measure of processor performance based on the number of instructions executed per second.

210. FLOPS (Floating Point Operations Per Second): A measure of computer performance, especially in scientific calculations that make heavy use of floating-point calculations.

211. Dennard Scaling: A scaling law which states that as transistors get smaller, their power density stays constant.

212. Dark Silicon: The portion of a chip that must remain powered off due to power and thermal constraints.

213. Roofline Model: A visual performance model used to provide performance estimates of computer kernels on multicore architectures.

214. Branch Misprediction Penalty: The cost in cycles when a branch prediction is incorrect and the pipeline must be flushed.

215. Processor Affinity: The assignment of a process to a specific CPU or set of CPUs.

Mastering these 201+ microprocessor terms won’t happen overnight, but neither did the construction of the processors themselves. Remember that understanding—not just memorization—is your goal. The board examiners don’t just want to see that you can recite definitions; they want proof that you grasp how these concepts interconnect to form the backbone of modern computing systems.

I recommend tackling these terms in small batches of 15-20 per study session, focusing on one section at a time. Create flashcards, explain concepts to classmates, or even record yourself explaining the more complex terms—teaching is often the best way to learn. Most importantly, practice applying these terms by solving previous board exam questions, which will help you recognize how examiners phrase questions around these concepts.

The engineering board exam is tough—we all know that. But with this comprehensive resource, you’re now equipped with the precise terminology that separates passing students from top performers. When you walk into that examination room, you’ll carry with you not just memorized definitions, but a genuine understanding of microprocessor fundamentals that will serve you throughout your engineering career.

Remember, the difference between stress and confidence on exam day often comes down to preparation. Bookmark this page, share it with your study group, and return to it regularly as your exam approaches. Your future self—the one with a newly minted engineering license—will thank you for putting in the work today.

Good luck on your board exam! If you found this guide helpful, be sure to check out our other exam preparation resources on Pinoybix.org to help you conquer every section of the engineering board exam.