Boolean Algebra: 101+ Essential Terms and Definitions for Engineering Board Exams

Let’s face it – Boolean Algebra can be overwhelming when you’re preparing for your board exams. Many engineering students struggle with this topic because textbooks often present it in abstract ways that don’t connect to practical applications. With limited study time and the pressure to master multiple subjects, memorizing these concepts can feel impossible.

I’ve been there too. After teaching engineering students for over a decade and working in the industry for seven years, I’ve seen firsthand how Boolean Algebra trips up even the brightest students. That’s why I’ve compiled this comprehensive guide of 105 essential terms and definitions that frequently appear in ECE, ECT board exams and Computer Engineering examinations.

This isn’t just another list of definitions. Each term is explained clearly with the exact technical language examiners look for, organized into logical sections that follow the way the concepts build upon each other. Whether you’re struggling with K-maps or getting confused between flip-flop types, this guide will become your go-to reference during those crucial weeks before your exam.

Bookmark this page now – you’ll want to review these definitions multiple times before exam day. Let’s turn Boolean Algebra from your biggest challenge into your highest-scoring section!

Basic Concepts and Operations

1. Boolean Algebra: A branch of algebra dealing with binary variables and logical operations that follow rules developed by George Boole.

2. Binary Variable: A variable that can only have two possible values: 0 (false) or 1 (true).

3. Logic Gate: A physical electronic device implementing a Boolean function, processing signals representing true or false values.

4. Boolean Function: A function that operates on binary variables and produces binary outputs according to defined rules.

5. Boolean Expression: A formula consisting of binary variables, constants (0 and 1), and logical operations.

6. Truth Table: A table showing all possible combinations of input values and their corresponding output values for a Boolean function.

7. AND Operation: A logical operation (·) that yields true (1) only when all inputs are true; otherwise false (0).

8. OR Operation: A logical operation (+) that yields true (1) when at least one input is true; otherwise false (0).

9. NOT Operation: A logical operation (̅ or ‘) that inverts the value of the input, changing true to false and false to true.

10. Literal: A variable or its complement in a Boolean expression.

11. Complement: The inverse or negation of a Boolean variable or expression; represented by a bar over the variable or an apostrophe.

12. Universal Set: In Boolean algebra, the universal set corresponds to 1 (true).

13. Empty Set: In Boolean algebra, the empty set corresponds to 0 (false).

Laws and Theorems

14. Idempotent Law: A Boolean variable ORed with itself or ANDed with itself equals itself. X + X = X and X · X = X.

15. Identity Law: Any variable ORed with 0 equals the variable, and any variable ANDed with 1 equals the variable. X + 0 = X and X · 1 = X.

16. Complement Law: X + X̅ = 1 and X · X̅ = 0, where X̅ is the complement of X.

17. Commutative Law: The order of variables doesn’t affect the result. X + Y = Y + X and X · Y = Y · X.

18. Associative Law: The grouping of variables doesn’t affect the result. (X + Y) + Z = X + (Y + Z) and (X · Y) · Z = X · (Y · Z).

19. Distributive Law: X · (Y + Z) = (X · Y) + (X · Z) and X + (Y · Z) = (X + Y) · (X + Z).

20. Absorption Law: X + (X · Y) = X and X · (X + Y) = X.

21. De Morgan’s First Theorem: The complement of a sum equals the product of complements. (X + Y)̅ = X̅ · Y̅.

22. De Morgan’s Second Theorem: The complement of a product equals the sum of complements. (X · Y)̅ = X̅ + Y̅.

23. Duality Principle: If a Boolean equation is valid, its dual is also valid, obtained by interchanging AND and OR operations and replacing 0s with 1s and vice versa.

24. Double Negation Law: The complement of a complement equals the original. (X̅)̅ = X.

25. Null Law: X + 1 = 1 and X · 0 = 0.

26. Consensus Theorem: XY + X̅Z + YZ = XY + X̅Z.

27. Shannon’s Expansion Theorem: Any Boolean function can be expressed as f(x₁,x₂,…,xₙ) = x₁·f(1,x₂,…,xₙ) + x̅₁·f(0,x₂,…,xₙ).

Boolean Expression Simplification

28. Canonical Form: Standard representation of a Boolean function as a sum of products (SOP) or product of sums (POS).

29. Sum of Products (SOP): Boolean expression formed by OR-ing several AND terms, also called disjunctive normal form.

30. Product of Sums (POS): Boolean expression formed by AND-ing several OR terms, also called conjunctive normal form.

31. Minterm: A product term in which all variables appear exactly once in either true or complemented form.

32. Maxterm: A sum term in which all variables appear exactly once in either true or complemented form.

33. Simplification: The process of reducing a Boolean expression to its simplest form with minimal terms.

34. Prime Implicant: A product term that cannot be combined with any other term to form a simpler term.

35. Essential Prime Implicant: A prime implicant that covers at least one minterm not covered by any other prime implicant.

36. Karnaugh Map (K-map): A graphical method for simplifying Boolean expressions by visually identifying adjacent minterms.

37. Adjacent Cells: Cells in a K-map that differ in exactly one variable, representing minterms that can be combined.

38. Quine-McCluskey Method: A tabular method for minimizing Boolean expressions, especially useful for functions with many variables.

39. Don’t Care Condition: Input combinations for which the output doesn’t matter, allowing for greater simplification.

40. Redundant Terms: Terms in a Boolean expression that can be eliminated without changing the function.

Digital Logic Implementation

41. NAND Gate: A logic gate that produces false output only if all inputs are true, equivalent to an AND gate followed by a NOT gate.

42. NOR Gate: A logic gate that produces true output only if all inputs are false, equivalent to an OR gate followed by a NOT gate.

43. XOR Gate: A logic gate that produces true output when the number of true inputs is odd.

44. XNOR Gate: A logic gate that produces true output when the number of true inputs is even.

45. Universal Gate: A logic gate (like NAND or NOR) from which any other logic gate can be constructed.

46. Buffer Gate: A logic gate that outputs the same logical value as its input.

47. Fan-in: The number of inputs a logic gate can accept.

48. Fan-out: The number of standard loads a logic gate can drive at its output.

49. Propagation Delay: The time delay between the application of an input signal and the appearance of the output signal.

50. Gate Equivalence: The implementation of one type of gate using other types of gates.

51. Logic Level: The voltage range representing either logic 0 or logic 1 in digital circuits.

52. Noise Margin: The amount by which a signal can vary without causing undesirable operation.

53. Transistor-Transistor Logic (TTL): A class of digital circuits based on transistors and resistors.

54. Complementary Metal-Oxide-Semiconductor (CMOS): A technology for constructing integrated circuits using complementary pairs of MOSFETs.

Combinational Logic Circuits

55. Combinational Circuit: A digital circuit whose output depends only on the current input values.

56. Half Adder: A combinational circuit that adds two binary digits and produces a sum and a carry.

57. Full Adder: A combinational circuit that adds three binary digits (two operands and a carry-in) and produces a sum and a carry-out.

58. Ripple Carry Adder: A digital adder that cascades full adders, with carry propagating through each stage.

59. Carry Look-ahead Adder: A faster adder that generates carry signals based on input signals without waiting for carry propagation.

60. Multiplexer (MUX): A combinational circuit that selects one of many input signals and forwards it to a single output line.

61. Demultiplexer (DEMUX): A combinational circuit that takes a single input and selects one of many output lines based on select signals.

62. Encoder: A combinational circuit that converts an active input line to a binary code.

63. Decoder: A combinational circuit that converts a binary code to an active output line.

64. Comparator: A combinational circuit that compares two binary numbers and determines their relationship.

65. Parity Generator: A circuit that adds an extra bit to data to make the number of 1s either even or odd.

66. Parity Checker: A circuit that checks if the number of 1s in data (including the parity bit) is even or odd.

67. Binary Coded Decimal (BCD): A system in which each decimal digit is represented by a four-bit binary code.

68. Seven-Segment Display Decoder: A circuit that converts binary input to signals driving a seven-segment display.

Sequential Logic and Memory Elements

69. Sequential Circuit: A digital circuit whose output depends on both current inputs and previous states.

70. Latch: A memory element with two stable states (set and reset) that maintains its state until explicitly changed.

71. SR Latch: A basic latch with Set and Reset inputs, potentially exhibiting a forbidden state when both inputs are active.

72. D Latch: A latch that captures and stores the value of the D (Data) input when enabled.

73. Flip-flop: A clocked memory element that changes state only at specified times determined by a clock signal.

74. D Flip-flop: A flip-flop that captures the value of D input at the clock edge and maintains it until the next clock edge.

75. JK Flip-flop: A versatile flip-flop with inputs J (Set) and K (Reset) that eliminates the forbidden state of the SR latch.

76. T Flip-flop: A flip-flop that toggles its state when the T input is 1 and maintains its state when T is 0.

77. Master-Slave Flip-flop: A flip-flop consisting of two latches in series, preventing race conditions.

78. Edge-triggered Flip-flop: A flip-flop that changes state only at either the rising or falling edge of a clock signal.

79. Asynchronous Input: Inputs to a sequential circuit that affect its state regardless of the clock signal.

80. Synchronous Input: Inputs to a sequential circuit that affect its state only in coordination with the clock signal.

81. Register: A group of flip-flops used to store multiple bits of information.

82. Shift Register: A register in which the stored bits can be shifted left or right.

83. Counter: A sequential circuit that goes through a predetermined sequence of states.

84. Ripple Counter: A counter where each flip-flop triggers the next flip-flop, potentially causing timing issues.

85. Synchronous Counter: A counter where all flip-flops are triggered by the same clock signal.

86. Up Counter: A counter that increments its value with each clock pulse.

87. Down Counter: A counter that decrements its value with each clock pulse.

88. Modulo-N Counter: A counter that cycles through N states before repeating.

Advanced Topics

89. Programmable Logic Array (PLA): An integrated circuit with programmable AND and OR planes used to implement Boolean functions.

90. Programmable Array Logic (PAL): A device with a programmable AND plane and a fixed OR plane.

91. Field-Programmable Gate Array (FPGA): An integrated circuit designed to be configured after manufacturing.

92. Hardware Description Language (HDL): A specialized language used to describe the structure and behavior of digital circuits.

93. VHDL: A hardware description language used in electronic design automation to describe digital systems.

94. Verilog: Another hardware description language used for modeling electronic systems.

95. Mealy Machine: A finite state machine whose output depends on both current state and current inputs.

96. Moore Machine: A finite state machine whose output depends only on the current state.

97. State Diagram: A graphical representation of a finite state machine showing states, transitions, and outputs.

98. State Table: A tabular representation of a finite state machine showing next states and outputs for each current state and input.

99. Race Condition: A situation where the output of a digital circuit depends on the sequence in which its inputs change.

100. Hazard: A temporary incorrect output due to propagation delays in a combinational circuit.

101. Static Hazard: A hazard that occurs when a signal should remain constant but momentarily changes.

102. Dynamic Hazard: A hazard that causes multiple transitions when there should be only one.

103. Boolean Satisfiability Problem (SAT): The problem of determining if there exists an assignment of values to variables that makes a Boolean formula true.

104. Minimization Algorithm: An algorithm that finds the simplest possible Boolean expression equivalent to a given function.

105. Reed-Muller Form: An alternative canonical form for Boolean functions using XOR and AND operations.

After reviewing these 105 Boolean Algebra terms and definitions, you’re now equipped with the essential knowledge that board examiners frequently test. Remember that understanding these concepts isn’t just about passing your exam – these are the fundamental building blocks that will serve you throughout your engineering career.

Many students waste precious study time searching through multiple resources, trying to piece together what’s important. I’ve consolidated everything you need right here, based on years of analyzing exam patterns and teaching thousands of engineering students who went on to pass their board exams.

Don’t make the mistake of simply memorizing these definitions. Take time to understand how concepts like De Morgan’s theorems connect to practical circuit design or how K-maps relate to Boolean expression simplification. The most successful exam takers can apply these principles to solve unfamiliar problems under time pressure.

In the weeks before your exam, revisit this guide regularly. Focus extra attention on the sections you find challenging – typically, Sequential Logic and Boolean Expression Simplification are the areas where points are most commonly lost.

Remember that confidence comes from preparation. Each time you review these terms, you’re building the mental framework that will help you process complex questions quickly during the exam. You’ve got this!

If you found this guide helpful, share it with your classmates and study group. And don’t forget to check out our other exam preparation resources here on Pinoybix.org – we’re committed to helping Filipino engineers achieve their professional dreams one exam at a time.

Good luck on your board exams!