Field Effect Transistor (FET) Terminology: 101+ Essential Terms for Engineering Board Exams

Are you struggling to memorize all those FET terms before your board exam? You’re not alone. Engineering students everywhere find semiconductor device terminology overwhelming, with confusing similarities between MOSFET and JFET concepts making study sessions frustrating and inefficient.

Field Effect Transistors represent one of the most challenging yet crucial topics in electronics engineering exams. Many students fail this section not because they don’t understand the concepts, but because they mix up terminology or miss subtle distinctions examiners love to test. I’ve seen countless well-prepared students lose valuable points on questions they actually understood conceptually.

This guide organizes over 100 essential FET terms into logical sections that match how board exams typically structure questions. Instead of endless rereading of textbook chapters, use this focused resource to:

• Quickly identify gaps in your terminology knowledge
• Understand key distinctions between similar-sounding terms
• Focus on the specific terminology examiners frequently test
• Build confidence with precise definitions that use proper engineering language

Whether you’re cramming the night before or planning your study schedule months ahead, this terminology guide will save you countless hours of textbook hunting and confusion. Let’s transform FET terminology from your biggest weakness into your secret weapon for exam success.

Basic FET Concepts and Structure

1. Field Effect Transistor (FET): A three-terminal semiconductor device that uses an electric field to control the flow of current in a channel, characterized by high input impedance and voltage-controlled operation.

2. Channel: The semiconductor region in a FET through which majority carriers flow from source to drain, with its conductivity controlled by the gate voltage.

3. Enhancement Mode: FET operational mode where the channel conductivity increases (enhances) when gate voltage is applied, starting from an initially non-conducting state.

4. Depletion Mode: FET operational mode where the channel is naturally conductive at zero gate voltage and becomes less conductive (depleted) as gate voltage is applied.

5. Majority Carriers: The predominant charge carriers in a semiconductor material (electrons in n-type, holes in p-type) responsible for current conduction in FETs.

6. Unipolar Device: Classification for FETs because current conduction involves only one type of charge carrier (either electrons or holes), unlike bipolar transistors.

7. JFET (Junction Field Effect Transistor): A FET type where the gate forms a reverse-biased PN junction with the channel to control current flow through depletion region modulation.

8. MOSFET (Metal-Oxide-Semiconductor FET): A FET type with an insulated gate structure where an oxide layer separates the gate from the semiconductor channel.

9. Substrate: The foundation semiconductor material upon which the FET structure is built, typically forming the body terminal in MOSFETs.

10. Gate: The control terminal in a FET that creates an electric field to modulate channel conductivity, determining the amount of current flow.

11. Source: The terminal in a FET from which majority carriers enter the channel, serving as the reference point for voltage measurements.

12. Drain: The terminal in a FET to which majority carriers flow through the channel from the source, typically held at a higher potential than the source.

JFET Specific Terms

13. N-Channel JFET: A JFET with an n-type semiconductor channel where electrons are the majority carriers, controlled by p-type gate regions.

14. P-Channel JFET: A JFET with a p-type semiconductor channel where holes are the majority carriers, controlled by n-type gate regions.

15. Gate-Channel Junction: The PN junction formed between the gate and channel in a JFET, operated in reverse bias to control channel width.

16. Pinch-Off Voltage (VP): The gate-to-source voltage at which the depletion region completely closes the channel in a JFET, reducing drain current to a minimum value.

17. IDSS (Saturation Current): The maximum drain current in a JFET when VGS = 0 and VDS is greater than the pinch-off voltage, representing the fully open channel condition.

18. Depletion Region: The area at the gate-channel junction depleted of mobile charge carriers, which expands with increasing reverse bias to control channel width.

19. Gate Leakage Current (IGSS): The small current that flows through the reverse-biased gate-channel junction in a JFET, typically in the nanoampere range.

20. Self-Bias: A JFET biasing technique using a source resistor to develop the appropriate negative gate-to-source voltage through voltage drop.

21. Voltage-Divider Bias: A JFET biasing method using resistors in a voltage divider configuration to set the gate voltage relative to ground.

22. Common-Source Configuration: A JFET circuit arrangement where the source terminal is common to both input and output signals, providing voltage gain.

MOSFET Specific Terms

23. Gate Oxide: The thin insulating layer (typically silicon dioxide) between the gate electrode and the semiconductor channel in a MOSFET.

24. Enhancement-Mode MOSFET: A MOSFET that requires gate voltage to form a conductive channel, with negligible drain current at zero gate voltage.

25. Depletion-Mode MOSFET: A MOSFET with a built-in channel that conducts at zero gate voltage and requires gate voltage to deplete the channel.

26. Threshold Voltage (VTH): The minimum gate-to-source voltage required to create a conductive channel in an enhancement-mode MOSFET.

27. N-Channel MOSFET (NMOS): A MOSFET with an n-type channel where electrons are the majority carriers, created between p-type substrate regions.

28. P-Channel MOSFET (PMOS): A MOSFET with a p-type channel where holes are the majority carriers, created between n-type substrate regions.

29. Body Effect: The phenomenon where the threshold voltage of a MOSFET changes due to potential difference between source and substrate.

30. Gate Capacitance: The capacitance formed between the gate electrode and the channel, affecting switching speed and frequency response.

31. Oxide Thickness: The dimension of the insulating oxide layer that separates the gate from the channel, influencing gate capacitance and threshold voltage.

32. Surface Inversion: The formation of a thin layer of minority carriers at the semiconductor surface beneath the gate oxide when sufficient gate voltage is applied.

33. CMOS (Complementary MOS): A technology combining both NMOS and PMOS transistors on the same substrate to create low-power digital circuits.

34. Source/Drain Diffusion: The process of creating heavily doped source and drain regions in a MOSFET through impurity diffusion.

35. Gate Polysilicon: The conductive polycrystalline silicon material commonly used for the gate electrode in MOSFET structures.

36. Lightly Doped Drain (LDD): A MOSFET structure with lightly doped regions between the channel and heavily doped drain areas to reduce hot electron effects.

FET Electrical Parameters and Characteristics

37. Transconductance (gm): The ratio of change in drain current to change in gate-source voltage, measuring the effectiveness of gate voltage in controlling drain current.

38. Output Conductance (gd): The ratio of change in drain current to change in drain-source voltage in the saturation region, ideally approaching zero.

39. Input Capacitance (Ciss): The sum of gate-to-source and gate-to-drain capacitances with the drain shorted to source for AC signals.

40. Output Capacitance (Coss): The sum of drain-to-source and gate-to-drain capacitances with the gate shorted to source for AC signals.

41. Reverse Transfer Capacitance (Crss): The gate-to-drain capacitance that contributes to feedback effects in amplifier circuits.

42. Early Voltage (VA): A parameter describing the finite output resistance of a FET in saturation, related to channel length modulation.

43. Channel Length Modulation: The phenomenon where the effective channel length decreases as drain voltage increases, causing drain current to increase slightly in saturation.

44. Cutoff Region: The operational state where the FET conducts minimal or no current due to insufficient gate-to-source voltage.

45. Linear Region: The operational state where drain current varies approximately linearly with drain-to-source voltage at a given gate voltage.

46. Saturation Region: The operational state where drain current remains relatively constant despite increases in drain-to-source voltage.

47. Gate-Source Cutoff Voltage (VGS(off)): The gate-source voltage at which the drain current reduces to a specified minimum value, effectively turning off the FET.

48. Forward Transconductance (gfs): The ratio of drain current change to gate-source voltage change under specified conditions, measuring amplification capability.

49. Drain-Source On-Resistance (RDS(on)): The resistance between drain and source terminals when the FET is fully turned on, critical for power applications.

50. Transfer Characteristic: The relationship between drain current and gate-source voltage at a constant drain-source voltage, showing how the FET responds to input signals.

51. Output Characteristic: The relationship between drain current and drain-source voltage at various gate-source voltages, showing different operating regions.

52. Voltage Gain (Av): The ratio of output voltage change to input voltage change in a FET amplifier circuit, typically the product of transconductance and load resistance.

Power FET Terms

53. Power MOSFET: A MOSFET designed to handle high power levels with features like vertical structure and optimized for low on-resistance and high switching speeds.

54. DMOS (Double-diffused MOS): A MOSFET fabrication technique using double diffusion to create short channels, commonly used in power devices.

55. VMOS (Vertical MOS): A power MOSFET structure with a V-shaped groove gate that increases current handling capability through vertical current flow.

56. UMOS (Trench MOS): A power MOSFET design using a U-shaped trench for the gate structure to increase channel density and reduce on-resistance.

57. LDMOS (Laterally Diffused MOS): A power MOSFET structure with asymmetric source and drain regions, optimized for high-frequency RF applications.

58. Avalanche Breakdown: A failure mechanism in power FETs where high electric fields cause rapid carrier multiplication and potentially destructive current flow.

59. Safe Operating Area (SOA): The defined boundary of voltage, current, and power within which a power FET can operate without damage.

60. Breakdown Voltage (BVDSS): The maximum drain-to-source voltage a FET can withstand before breakdown occurs with the gate shorted to the source.

61. Maximum Drain Current (ID(max)): The highest continuous drain current a power FET can conduct without exceeding thermal limitations.

62. Thermal Resistance (RθJA): A measure of how efficiently a FET package transfers heat from the junction to ambient air, specified in °C/W.

63. Junction Temperature (TJ): The temperature at the semiconductor junction within a FET, which must remain below maximum rated values.

64. Figure of Merit (FOM): A performance metric for power FETs, often calculated as the product of on-resistance and gate charge, with lower values being better.

65. Gate Charge (Qg): The total charge required to turn on a power MOSFET, affecting switching speed and driver requirements.

66. Miller Charge (Qgd): The charge required to change the gate-to-drain capacitance voltage during switching, a significant component of switching losses.

FET Applications and Circuits

67. Source Follower: A FET circuit configuration where output is taken from the source terminal, providing high input impedance and voltage gain less than unity.

68. Common-Drain Configuration: Another name for the source follower circuit, where the drain is common to both input and output circuits.

69. Common-Gate Configuration: A FET circuit arrangement where the gate terminal is common to both input and output signals, offering good high-frequency performance.

70. Cascode Configuration: A circuit combining common-source and common-gate stages to reduce Miller effect and improve high-frequency performance.

71. MOSFET Switch: An application using MOSFETs as electronic switches, leveraging their low on-resistance and high off-resistance properties.

72. CMOS Inverter: A basic digital circuit using complementary NMOS and PMOS transistors to implement logical NOT operations with low power consumption.

73. Transmission Gate: A CMOS circuit using parallel NMOS and PMOS transistors to pass analog or digital signals bidirectionally when enabled.

74. Level Shifter: A circuit using FETs to translate signals between different voltage levels in mixed-voltage systems.

75. Current Mirror: A FET circuit that copies a reference current to produce one or more identical currents, used in analog integrated circuits.

76. Operational Transconductance Amplifier (OTA): An amplifier circuit using FETs that converts input voltage to output current, with transconductance as the gain parameter.

77. Bootstrapping: A technique using capacitive feedback to dynamically increase the effective gate-source voltage of a FET beyond the supply voltage.

78. Charge Pump: A circuit using FETs and capacitors to generate voltages higher than the supply voltage or negative voltages.

79. Subthreshold Operation: Using MOSFETs in the region below threshold voltage where they exhibit exponential current-voltage characteristics, useful for low-power applications.

80. Voltage-Controlled Resistor: An application using a FET in the triode region to function as a resistor whose value is controlled by the gate voltage.

FET-Based Integrated Circuits

81. SRAM Cell: A static random-access memory cell typically constructed using six MOSFETs to store a bit without need for refreshing.

82. DRAM Cell: A dynamic random-access memory cell using a single MOSFET and capacitor to store a bit, requiring periodic refreshing.

83. Flash Memory: Non-volatile memory technology using floating-gate MOSFETs to store information by trapping charge on an isolated gate.

84. Floating Gate: An isolated conductive region within a specialized MOSFET structure used in flash memory to store charge for extended periods.

85. Analog Switch: An integrated circuit using MOSFETs to connect or disconnect signal paths based on a control voltage.

86. Gate Array: A prefabricated integrated circuit with unconnected MOSFETs that can be customized by adding metal interconnections.

87. Standard Cell: A predefined circuit building block composed of MOSFETs with known electrical characteristics used in ASIC design.

88. ASIC (Application-Specific Integrated Circuit): A custom integrated circuit using FETs designed for a specific application rather than general-purpose use.

89. Logic Gate: A fundamental digital building block implemented using MOSFETs to perform Boolean logic operations.

90. Flip-Flop: A sequential logic circuit built with MOSFETs that can store one bit of state information.

91. MOSFET Scaling: The process of reducing MOSFET dimensions to improve performance, increase density, and reduce power consumption in integrated circuits.

Advanced FET Technologies

92. FinFET: A 3D MOSFET structure where the channel forms a fin-like feature extending vertically from the substrate, reducing short-channel effects.

93. HEMT (High Electron Mobility Transistor): A FET using heterojunctions between different semiconductor materials to create a channel with very high electron mobility.

94. MESFET (Metal-Semiconductor FET): A FET using a metal-semiconductor Schottky junction instead of a p-n junction or insulated gate to control channel conductivity.

95. SOI (Silicon-On-Insulator): A MOSFET technology where transistors are fabricated in a thin silicon layer on top of an insulating substrate to reduce parasitic capacitance.

96. GAA (Gate-All-Around) FET: An advanced MOSFET structure where the gate material surrounds the channel on all sides for better electrostatic control.

97. TFET (Tunnel FET): A transistor based on quantum tunneling rather than thermionic emission, offering potential for ultra-low power operation.

98. IGBT (Insulated Gate Bipolar Transistor): A hybrid device combining MOSFET input characteristics with bipolar transistor output capabilities for power applications.

99. GaN (Gallium Nitride) FET: A high-electron-mobility transistor made with gallium nitride, offering superior high-frequency and high-power performance.

100. SiC (Silicon Carbide) MOSFET: A power MOSFET using silicon carbide semiconductor material to achieve higher breakdown voltage and better thermal performance.

101. QFET (Quantum FET): An experimental transistor exploiting quantum mechanical effects for computation, representing potential future technology.

102. UTB (Ultra-Thin Body) FET: A MOSFET with an extremely thin semiconductor channel to improve electrostatic control and reduce short-channel effects.

103. DEPFET (Depleted P-channel FET): A specialized FET structure combining a MOSFET with a sideways depleted p-channel and an integrated sensing node.

104. JLNT (Junctionless Nanowire Transistor): A FET design without conventional p-n junctions, using only differently doped regions to control current flow.

105. MuGFET (Multiple-Gate FET): A category of FETs with more than one gate controlling the channel, including dual-gate, tri-gate, and gate-all-around structures.

Let’s face it – memorizing 100+ FET terms won’t suddenly make semiconductor physics your favorite subject. But having this terminology mastered will make a real difference in your board exam score, potentially turning a failing grade into a passing one or a passing grade into an excellent one.

I’ve seen engineering students walk into exams confident about their conceptual understanding only to freeze when encountering unfamiliar terminology in questions. Don’t let that be you. Print this guide, highlight the terms you struggle with, and tackle them systematically. Create flashcards for the most challenging ones. Quiz yourself regularly.

Remember three key strategies as exam day approaches:

1. Focus on relationships between terms, not just isolated definitions
2. Practice explaining each term in your own words to test true understanding
3. Connect terms to actual circuit applications you’ve worked with in lab

The difference between top-scoring students and average performers often comes down to precision in understanding and applying terminology. Your future employer won’t quiz you on the definition of “transconductance,” but mastering these terms now builds the foundation for everything that follows in your engineering career.

Take this guide with you during your study sessions. Refer to it when working on practice problems. And most importantly, believe that you can master this material – because with the right resources and approach, you absolutely can.